1. Field of the Invention
The present invention relates generally to the field of semiconductor devices and more particularly to Back-End of Line (BEoL) interconnect structures and methods for their fabrication.
2. Description of the Prior Art
Increased semiconductor device performance can be achieved, at least in part, through the further miniaturization of features such as transistors. Decreased feature sizes, and decreased spacings between features, allow more features to be placed in a unit area for greater device performance. Back-End of Line (BEoL) interconnect structures include conductive lines that connect to the features. As feature densities increase, the widths of the conductive lines, and the spacings between the conductive lines also need to scale smaller.
One problem that is encountered as the conductive lines within BEoL interconnect structures are made more narrow pertains to the positioning of vias relative to those conductive lines. Ideally, each via “lands” on a conductive line. However, if vias and conductive lines are sufficiently misaligned, vias will land on the dielectric material between the conductive lines and therefore fail to connect to conductive lines. If a via lands partially on a conductive line, and partially on the dielectric material, although an electrical connection is made between the conductive line and the via, copper can deleteriously diffuse from the via into the dielectric material. Additionally, the reduced area of the electrical connection becomes an area of higher current density which accelerates void formation in the via and can lead to failures and reduced yields. Accordingly, as the conductive lines are made more narrow, landing vias on the conductive lines requires greater alignment precision.
Also, as conductive lines within BEoL interconnect structures are made more narrow, the overall dielectric constant of the interconnect structure needs to be reduced. The overall dielectric constant is an average, however, over the many dielectric layers in the interconnect structure. Some of these dielectric layers, though thin, are characterized by undesirably large dielectric constants that raise the overall dielectric constant.
What is desired, therefore, are methods for aligning vias with more narrow conductive lines in BEoL interconnect structures, and BEoL interconnect structures characterized by lower overall dielectric constants, increased yields, and greater reliability.